Optimizing decoupling capacitors in 3D circuits for power grid integrity

Pingqiang Zhou; Karthikk Sridharan; Sachin S. Sapatnekar

doi:10.1109/MDT.2009.120

Optimizing decoupling capacitors in 3D circuits for power grid integrity

Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

21 Scopus citations

Abstract

Editor's note:This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design.

Original language	English (US)
Pages (from-to)	15-25
Number of pages	11
Journal	IEEE Design and Test of Computers
Volume	26
Issue number	5
DOIs	https://doi.org/10.1109/MDT.2009.120
State	Published - 2009

Keywords

3D integration
CMOS decap
CMOS integrated circuits
Capacitance
Decoupling capacitors
Design and test
MIM decap
Noise
Optimization
Power grid
Power grids
Three dimensional displays
Tiles

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Optimizing decoupling capacitors in 3D circuits for power grid integrity

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