Optimizing decoupling capacitors in 3D circuits for power grid integrity

Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

Editor's note:This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design.

Original languageEnglish (US)
Pages (from-to)15-25
Number of pages11
JournalIEEE Design and Test of Computers
Volume26
Issue number5
DOIs
StatePublished - Nov 6 2009

Keywords

  • 3D integration
  • CMOS decap
  • CMOS integrated circuits
  • Capacitance
  • Decoupling capacitors
  • Design and test
  • MIM decap
  • Noise
  • Optimization
  • Power grid
  • Power grids
  • Three dimensional displays
  • Tiles

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