Optimizing large multiphase level-clocked circuits

Naresh Maheshwari, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

Retiming is a powerful technique for optimizing sequential circuits. The transparent nature of level sensitive latches enables level-clocked circuits to operate faster and require fewer memory elements than edge-triggered circuits. However, this transparency makes the operation of level-clocked circuits very complex, and optimization of level-clocked circuits is a difficult task. This work presents efficient algorithms for retiming large level-clocked circuits. To provide us with a simpler view of the operation of level-clocked circuits, we present the relationship between retiming and clock skew optimization. We then utilize this relationship to develop efficient retiming algorithms for period and area optimization. For period optimization, we present an algorithm which produces near-optimal results, but is significantly faster than the traditional algorithms. In this approach, we first calculate the best possible clock period and the amount of motion required for each latch. The latches are then relocated in an attempt to achieve this period. Area, as measured by the number of latches in the circuit can be optimized by solving a linear program. We apply efficient pruning techniques to reduce the size of this linear program, while preserving optimality. Since generating the linear program is a major part of the computational requirements of minarea retiming, we present techniques for efficient generation of the reduced linear program. This enables us to perform area optimization of large circuits clocked by symmetric multiphase clocks in very reasonable time, without sacrificing optimality. We present results on circuits with up to 56 000 gates, performing period optimization in under 20 s and area optimization in under 1.5 h.

Original languageEnglish (US)
Pages (from-to)1249-1264
Number of pages16
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume18
Issue number9
DOIs
StatePublished - 1999

Bibliographical note

Funding Information:
Manuscript received October 23, 1997; revised February 18, 1999. This work was supported in part by the National Science Foundation (NSF) award MIP-9502556, a Lucent Technologies DAC Graduate Scholarship, and an Iowa State University Computation Center Grant. This paper was recommended by Associate Editor M. Papaefthymiou.

Fingerprint Dive into the research topics of 'Optimizing large multiphase level-clocked circuits'. Together they form a unique fingerprint.

Cite this