Order-configurable programmable power-efficient FIR filters

Chong Xu, Chang Yi Wang, Keshab K Parhi

Research output: Contribution to conferencePaperpeer-review

13 Scopus citations

Abstract

We present a novel VLSI implementation of an order-configurable, coefficient-programmable, and power-efficient FIR filter architecture. This single-chip architecture contains 4 multiply-add functional units and each functional unit can have up to 8 multiply-add operations time-multiplexed (or folded) onto it. Thus one chip can be used to realize FIR filters with lengths ranging from 1 to 32 and multiple chips can be cascaded for higher order filters. To achieve power-efficiency, an on-chip phase locked loop (PLL) is used to automatically generate the minimum voltage level to achieve the required sample rate. Within the PLL, a novel programmable divider and a voltage level shifter are used in conjunction with the clock rate to control the internal supply voltage. Simulations show that this chip can be operated at a maximum clock rate of 100 MHz (folding factor of 1 or filter length of 4). When operated at 10 MHz, this chip only consumes 27.45 mW using an automatically set internal supply voltage of 2 V. For comparison, when the chip is operated at 10 MHz and 5 V, it consumes 109.24 mW. At 100 MHz, the chip consumes 891 mW with a 4.5 V supply that is automatically generated by the PLL. This design has been implemented using Mentor Graphics tools for an 8-bit word-length and 1.2 μm CMOS technology.

Original languageEnglish (US)
Pages357-361
Number of pages5
StatePublished - Dec 1 1996
EventProceedings of the 1996 3rd International Conference on High Performance Computing, HiPC - Trivandrum, India
Duration: Dec 19 1996Dec 22 1996

Other

OtherProceedings of the 1996 3rd International Conference on High Performance Computing, HiPC
CityTrivandrum, India
Period12/19/9612/22/96

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