Overscaling-friendly timing speculation architectures

Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (BTWC) design approaches based on timing speculation (TS) have recently gained ground as an alternative to traditional designs by allowing processors to be designed for the average case and still maintain high yields. In this paper, we characterize the behavior of TS-based designs in the face of voltage overscaling (or undervolting). We show that the power benefits of TS due to voltage overscaling are greatly determined by the design of the circuit architecture. The benefits are small if the underlying circuit has a small range of timing paths, as such circuits produce catastrophic failures in the face of voltage overscaling. Benefits may be limited even for circuits with a wide range of timing paths, due to short path and long path constraints imposed by TS techniques like Razor and EDS. In general, TS-based designs are shown to be not very effective in the face of aggressive voltage overscaling. We propose two techniques to alleviate the limitations of TS architectures. The two techniques - using adaptable skew for TS and decoupling pipeline stages using local asynchrony - are shown to be effective at reducing both the number of uncorrectable errors in the face of voltage overscaling and the power consumption of the TS architecture.