Parallel architecture for a multiple-input fuzzy logic controller

Marian S. Stachowicz, Janos Grantner, Larry L. Kinney

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A hardware accelerator that performs fuzzy learning, fuzzy inference, and defuzzification strategy computations is presented. The hardware is based on two-valued logic. A universal space of 25 elements with five levels each is supported. To achieve a high processing rate for real-time applications, the basic units of the accelerator are connected in a four-level pipeline. The accelerator can receive two parallel fuzzy data as inputs. A flag will be set if the fuzzy model R(u,w), constructed in a learning process, exhibits the property as follows: for all (u,w) belonging to the set U×W, R(u,w) = 1. At a clock rate of 20 MHz, the accelerator can perform more than 1,400,000 fuzzy logic inferences per second on multi-dimensional fuzzy data.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsGautam Biswas
PublisherPubl by Int Soc for Optical Engineering
Pages137-145
Number of pages9
ISBN (Print)0819408727
StatePublished - Jan 1 1992
EventApplications of Artificial Intelligence X: Knowledge-Based Systems - Orlando, FL, USA
Duration: Apr 22 1992Apr 24 1992

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume1707
ISSN (Print)0277-786X

Other

OtherApplications of Artificial Intelligence X: Knowledge-Based Systems
CityOrlando, FL, USA
Period4/22/924/24/92

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