Parallel-pipelined radix-22 FFT architecture for real valued signals

Manohar Ayinala, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

This paper presents a novel parallel-pipelined architecture for the computation of real valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the redundancy of some computations with respect to complex FFT along with low multiplicative complexity of the radix-2 2 architecture. Folding transformation is used to derive a novel parallel-pipelined architecture by exploiting the redundancy in the modified flow graph. The proposed parallel architecture requires log4N - 1 complex multipliers and N - 1 complex delay elements.

Original languageEnglish (US)
Title of host publicationConference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
Pages1274-1278
Number of pages5
DOIs
StatePublished - Dec 1 2010
Event44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 - Pacific Grove, CA, United States
Duration: Nov 7 2010Nov 10 2010

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
CountryUnited States
CityPacific Grove, CA
Period11/7/1011/10/10

Keywords

  • FFT
  • Folding
  • Parallel Processing
  • Pipelining
  • Real Signals
  • radix-2

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