To achieve additional speedup in rank order and stack filter architectures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential when the architecture reaches the throughput limits caused by the underlying technology. A trivial block structure repeats a single input, single output structure to generate a multiple input, multiple output structure and can achieve speedups equal to the block size (or the number of multiple outputs). Unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure. The authors introduce a systematic method for applying block processing to the rank order and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced. Furthermore, block processing is important for the generation of low power designs. Trivial block structures generate low power designs up to a certain limit. The authors demonstrate how block structures with shared substructures are used to generate designs with arbitrarily low power.
|Original language||English (US)|
|Title of host publication||Proceedings of International Conference on Application Specific Array Processors, ASAP 1993|
|Editors||Benjamin Wah, Luigi Dadda|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||12|
|State||Published - 1993|
|Event||1993 International Conference on Application Specific Array Processors, ASAP 1993 - Venice, Italy|
Duration: Oct 25 1993 → Oct 27 1993
|Name||Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors|
|Conference||1993 International Conference on Application Specific Array Processors, ASAP 1993|
|Period||10/25/93 → 10/27/93|
Bibliographical noteFunding Information:
This research was supported in paru by an AT&T under mutract number N00014-91-1-100S.
© 1993 IEEE.
Copyright 2019 Elsevier B.V., All rights reserved.