Abstract
Turbo codes are one of the most powerful error correcting codes. The VLSI implementation of Turbo codes for higher decoding speed requires use of parallel architectures. This paper explores the design spaces of both serial and parallel MAP decoders using graphical analysis. Several existing designs are compared, and three new parallel decoding schemes are presented.
| Original language | English (US) |
|---|---|
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| State | Published - Sep 7 2004 |