This paper presents high-performance encoder and decoder architectures for a class of Low Density Parity Check (LDPC) codes. The codes considered here are based on the Parallely Concatenated Parity Check encoder structure. A major advantage of these codes is that the generator matrix and the parity check matrix are both sparse, which leads to efficient VLSI implementations for the encoder and the decoder. Our designs use 6-bit quantization with a code rate of 8/9 and a block size of 576 bits. An evaluation of the speed and hardware complexity is given, and simulation results for the bit error rate are obtained.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 2002|