Parallel VLSI architectures for a class of LDPC codes

Sungwook Kim, Gerald E Sobelman, Jaekyun Moon

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


This paper presents high-performance encoder and decoder architectures for a class of Low Density Parity Check (LDPC) codes. The codes considered here are based on the Parallely Concatenated Parity Check encoder structure. A major advantage of these codes is that the generator matrix and the parity check matrix are both sparse, which leads to efficient VLSI implementations for the encoder and the decoder. Our designs use 6-bit quantization with a code rate of 8/9 and a block size of 576 bits. An evaluation of the speed and hardware complexity is given, and simulation results for the bit error rate are obtained.

Original languageEnglish (US)
Pages (from-to)93-96
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 2002

Fingerprint Dive into the research topics of 'Parallel VLSI architectures for a class of LDPC codes'. Together they form a unique fingerprint.

Cite this