Performance analysis of III-V materials in a double-gate nano-MOSFET

Kurtis D. Cantley; Yang Liu; Himadri S. Pal; Tony Low; Shaikh S. Ahmed; Mark S. Lundstrom

doi:10.1109/IEDM.2007.4418877

Performance analysis of III-V materials in a double-gate nano-MOSFET

Kurtis D. Cantley, Yang Liu, Himadri S. Pal, Tony Low, Shaikh S. Ahmed, Mark S. Lundstrom

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

33 Scopus citations

Abstract

Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp³d⁵s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra-thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

Original language	English (US)
Article number	4418877
Pages (from-to)	113-116
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2007.4418877
State	Published - 2007
Event	2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: Dec 10 2007 → Dec 12 2007

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@article{ea5fdfa3f2ba409ca73073cd7844a116,

title = "Performance analysis of III-V materials in a double-gate nano-MOSFET",

abstract = "Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra-thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.",

author = "Cantley, {Kurtis D.} and Yang Liu and Pal, {Himadri S.} and Tony Low and Ahmed, {Shaikh S.} and Lundstrom, {Mark S.}",

year = "2007",

doi = "10.1109/IEDM.2007.4418877",

language = "English (US)",

pages = "113--116",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Electron Devices Meeting, IEDM ; Conference date: 10-12-2007 Through 12-12-2007",

}

TY - JOUR

T1 - Performance analysis of III-V materials in a double-gate nano-MOSFET

AU - Cantley, Kurtis D.

AU - Liu, Yang

AU - Pal, Himadri S.

AU - Low, Tony

AU - Ahmed, Shaikh S.

AU - Lundstrom, Mark S.

PY - 2007

Y1 - 2007

N2 - Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra-thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

AB - Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra-thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

UR - http://www.scopus.com/inward/record.url?scp=50249158622&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249158622&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2007.4418877

DO - 10.1109/IEDM.2007.4418877

M3 - Conference article

AN - SCOPUS:50249158622

SN - 0163-1918

SP - 113

EP - 116

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

M1 - 4418877

T2 - 2007 IEEE International Electron Devices Meeting, IEDM

Y2 - 10 December 2007 through 12 December 2007

ER -

Performance analysis of III-V materials in a double-gate nano-MOSFET

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