Nian Feng Tzeng, Pen Chung Yew, Chuan Qi Zhu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


It has been shown that fault-tolerant capabilities of a multistage interconnection network can be achieved via a simple scheme that provides redundant paths between each input/output pair of the network. The performance of such a network is analyzed. An analytical model is used to evaluate the bandwidth of the network operating under both fault-free and fault-present conditions. It has hardware complexity of O(N log//2 N) but can attain bandwidth comparable to a crossbar switch. Simulations are utilized to explore the average delay when buffers are incorporated into the network. A threshold value is assigned to buffers to regulate the traffic in the network. Better network delay can be achieved by controlling the threshold value. In addition, performance degradation caused by a single fault in a network is investigated.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsDouglas DeGroot
Number of pages8
ISBN (Print)0818606371
StatePublished - Dec 1 1985

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

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