Abstract
Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-world-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.
Original language | English (US) |
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Title of host publication | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors |
Publisher | IEEE |
Pages | 149-160 |
Number of pages | 12 |
State | Published - Jan 1 2000 |
Event | 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors - Boston, MA, USA Duration: Jul 10 2000 → Jul 12 2000 |
Other
Other | 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors |
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City | Boston, MA, USA |
Period | 7/10/00 → 7/12/00 |