One of the powerful yet simple algorithms to decode trellis codes as well as to combat intersymbol interference (ISI) is the parallel decision-feedback decoding algorithm. However, for high-speed applications, such as Gigabit Ethernet over copper (1000BASE-T), the design and implementation of a parallel decision-feedback decoder (PDFD) is challenging due to the long critical path in the decoder structure. Straightforward pipelined designs usually introduce significant hardware overhead. To solve these problems, in this paper, first, based on an optimized scheduling of the computations in the parallel decision-feedback decoding algorithm, a low-complexity pipelined PDFD is proposed. Next, a novel retiming and reformulation technique is presented for the decision-feedback unit (DFU) in the PDFD, which can remove the DFU from the critical path of the PDFD with negligible hardware overhead. Based on these two techniques, two modified low-complexity pipelined PDFDs are derived. Compared with similar designs in the literature, the proposed design can reduce hardware overhead by 60% while achieving similar speed-up for Gigabit Ethernet systems. The savings are even greater for a pulse amplitude modulation (PAM) system with larger constellation.
Bibliographical noteFunding Information:
Manuscript received November 5, 2004; revised February 25, 2006. The associate editor coordinating the review of this manuscript and approving it for publication was Dr. Shuvra S. Bhattacharyya. This research was supported in part by the National Science Foundation by the grant number CCF-0429979.
- Decision-feedback equalizers
- Parallel decision-feedback decoding
- Pipeline processing
- Trellis-coded modulation
- Viterbi decoding