Power comparison of SRT and GST dividers

Generally divider algorithms can be separated into two different kinds of algorithms, the Multiplicative Algorithms (MA) and the Iterative Digit Recurrence Algorithms (IDRA). The number of iterations of the MA and IDRA are proportional to log₂ (word-length) and the word-length, respectively. However every iteration of the MA consists of two multiplications and one addition, while the iteration period time of the IDRA only consists of one addition. The IDRA includes the SRT approach (named after Sweeney, Robertson and Tocher) which does not require prescaling, and the GST (generalized Svoboda and Tung) approach which requires prescaling of the operands. The iteration period of the GST is much smaller due to the fact that the GST only examines three bits (compared to 14 in the SRT) to predict the next quotient digit (for a minimally redundant radix-4 digit set). Due to this reason, the overall latency of the GST-divider is shorter. Alternatively, by fixing the latency, the supply voltage of the GST can be reduced, resulting in a low power implementation. Thus, the GST is more suitable for low latency and low power applications.