Practical analysis of clock jitter reduction techniques under power supply noise for continuous-time delta-sigma modulators

Lowpass continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects and various techniques have been proposed to cope with them in the past years. While three major techniques, switched-capacitor-resistor, switched-shaped-current and fixed-width pulse, are very effective to reduced clock jitter effects in theory, intrinsic device noise and external power supply noise may still limit their effectiveness in practice. In this paper, we perform detailed noise analysis of the three techniques to study their limits under external power supply noise as it is typically dominant and also to make a quantitative and practical comparison. It is found that the fixed-width pulse feedback technique may have a favorable edge among them for high frequency modulator designs, whereas switched-capacitor-resistor and switched-shaped-current techniques are more preferable in low to medium frequency modulator designs.