Abstract
A run-time leakage reduction technique for SRAM caches considers architecture and behavior to achieve an optimal tradeoff between overhead energy and leakage savings. A 16kB SRAM shows a 94.2% cell leakage reduction with a 2% performance penalty. Fabricated in a 0.18μm 6M CMOS process, the 3.2mm×2.9mm die also shows 25% improvement in read stability.
Original language | English (US) |
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Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
Volume | 48 |
State | Published - 2005 |
Event | 2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: Feb 6 2005 → Feb 10 2005 |
Other
Other | 2005 IEEE International Solid-State Circuits Conference, ISSCC |
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Country/Territory | United States |
City | San Francisco, CA |
Period | 2/6/05 → 2/10/05 |