PVT-aware leakage reduction for on-die caches with improved read stability

Chris H. Kim, Jae Joon Kim, Ik Joon Chang, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A run-time leakage reduction technique for SRAM caches considers architecture and behavior to achieve an optimal tradeoff between overhead energy and leakage savings. A 16kB SRAM shows a 94.2% cell leakage reduction with a 2% performance penalty. Fabricated in a 0.18μm 6M CMOS process, the 3.2mm×2.9mm die also shows 25% improvement in read stability.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
StatePublished - 2005
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 6 2005Feb 10 2005

Other

Other2005 IEEE International Solid-State Circuits Conference, ISSCC
Country/TerritoryUnited States
CitySan Francisco, CA
Period2/6/052/10/05

Fingerprint

Dive into the research topics of 'PVT-aware leakage reduction for on-die caches with improved read stability'. Together they form a unique fingerprint.

Cite this