Reconfigurable baseband processing architecture for communication

W. Q. Lu, S. Zhao, X. F. Zhou, J. Y. Ren, Gerald E Sobelman

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

Original languageEnglish (US)
Pages (from-to)63-72
Number of pages10
JournalIET Computers and Digital Techniques
Volume5
Issue number1
DOIs
StatePublished - Jan 1 2011

Fingerprint

Dive into the research topics of 'Reconfigurable baseband processing architecture for communication'. Together they form a unique fingerprint.

Cite this