Reconfigurable shuffle network design in LDPC decoders

Tang Jun, Tejas Bhatt, Vishwas Sundaramurthy, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Scopus citations

Abstract

Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the re-configurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. In this paper, we propose an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Pages81-86
Number of pages6
DOIs
StatePublished - Dec 1 2006
EventIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 - Steamboat Springs, CO, United States
Duration: Sep 11 2006Sep 13 2006

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

OtherIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
CountryUnited States
CitySteamboat Springs, CO
Period9/11/069/13/06

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