TY - GEN
T1 - Reconfigurable shuffle network design in LDPC decoders
AU - Jun, Tang
AU - Bhatt, Tejas
AU - Sundaramurthy, Vishwas
AU - Parhi, Keshab K
PY - 2006
Y1 - 2006
N2 - Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the re-configurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. In this paper, we propose an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.
AB - Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the re-configurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. In this paper, we propose an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size larger than the Benes network input size, the proposed algorithm can be extended to obtain the cyclic shift in multiple stages. Compared with the direct implementation of m m-to-1 multiplexers, the proposed algorithm achieves significant savings on area and routing complexity.
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U2 - 10.1109/ASAP.2006.60
DO - 10.1109/ASAP.2006.60
M3 - Conference contribution
AN - SCOPUS:34547406193
SN - 0769526829
SN - 9780769526829
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 81
EP - 86
BT - Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
T2 - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Y2 - 11 September 2006 through 13 September 2006
ER -