This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.