Abstract
Retiming is a powerful technique for delay and area optimization that operates by relocating the flip-flops in a circuit. This movement of flip-flops in control logic changes the state encoding of finite state machines, requiring the preservation of initial (reset) states. Unfortunately, traditional retiming algorithms pay no regard to maintaining the initial state. While some work has been carried out on finding a retiming of a circuit with equivalent initial states, it has concentrated on achieving a specified clock period without regard to the number of flip-flops. However, if the number of flip-flops is not explicitly minimized the retimed circuit may have a very large number of flip-flops. This work targets the problem of minimizing the number of flip-flops in control logic subject to a specified clock period and with a guarantee of an equivalent initial state. The problem is formulated as a mixed-integer linear program and bounds on the retiming variables are used to guarantee an equivalent initial state. These bounds also lead to a simple method for calculating an equivalent initial state for the retimed circuit. The mixed-integer linear program formulation is capable of modeling the maximum sharing of different types of flip-flops at the fanout of a gate. Experimental results on circuits of up to 9000 gates and are shown to be close to a (perhaps unachievable) lower bound.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 33-53 |
| Number of pages | 21 |
| Journal | Integration, the VLSI Journal |
| Volume | 28 |
| Issue number | 1 |
| DOIs | |
| State | Published - Sep 1999 |
Bibliographical note
Funding Information:Sachin Sapatnekar (S'86–M'93) received the B.Tech. degree from the Indian Institute of Technology, Bombay in 1987, the M.S. degree from Syracuse University in 1989, and the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992. He worked at Texas Instruments Inc., Dallas, TX in 1990 and at Intel Corporation, Santa Clara, CA in 1997. From 1992 to 1997, he was an assistant professor in the Department of Electrical and Computer Engineering at Iowa State University. He is currently an associate professor in the Department of Electrical Engineering at the University of Minnesota. He has coauthored the books, “Design Automation for Timing-Driven Layout Synthesis” and “Sequential Timing Analysis and Optimization,” both published by Kluwer Academic Publishers, Boston, MA. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing and as a program committee member for several conferences. He is a recipient of the NSF Career Award and Best Paper awards at DAC-97 and ICCD-98.