Retiming control logic

Naresh Maheshwari, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review


Retiming is a powerful technique for delay and area optimization that operates by relocating the flip-flops in a circuit. This movement of flip-flops in control logic changes the state encoding of finite state machines, requiring the preservation of initial (reset) states. Unfortunately, traditional retiming algorithms pay no regard to maintaining the initial state. While some work has been carried out on finding a retiming of a circuit with equivalent initial states, it has concentrated on achieving a specified clock period without regard to the number of flip-flops. However, if the number of flip-flops is not explicitly minimized the retimed circuit may have a very large number of flip-flops. This work targets the problem of minimizing the number of flip-flops in control logic subject to a specified clock period and with a guarantee of an equivalent initial state. The problem is formulated as a mixed-integer linear program and bounds on the retiming variables are used to guarantee an equivalent initial state. These bounds also lead to a simple method for calculating an equivalent initial state for the retimed circuit. The mixed-integer linear program formulation is capable of modeling the maximum sharing of different types of flip-flops at the fanout of a gate. Experimental results on circuits of up to 9000 gates and are shown to be close to a (perhaps unachievable) lower bound.

Original languageEnglish (US)
Pages (from-to)33-53
Number of pages21
JournalIntegration, the VLSI Journal
Issue number1
StatePublished - Sep 1999

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