Robust gate sizing by geometric programming

Jaskirat Singh, Vidyasagar Nookala, Zhi Quan Luo, Sachin Sapatnekar

Research output: Contribution to journalConference articlepeer-review

87 Scopus citations

Abstract

We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a Geometric Program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over die traditional detcrministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area, has fewer timing violations.

Original languageEnglish (US)
Article number19.2
Pages (from-to)315-320
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

Keywords

  • Geometric Program
  • Posynomial
  • Uncertainty ellipsoid

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