Selective epitaxial growth of silicon for vertical diode application

Kong Soo Lee, Dae Han Yoo, Jae Jong Han, Yong Woo Hyung, Seok Sik Kim, Chang Jin Kang, Hong Sik Jeong, Joo Tae Moon, Hyunho Park, Hanwook Jeong, Kwang Ryul Kim, Byoungdeog Choi

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6 Scopus citations

Abstract

Selectivity control in silicon selective epitaxial growth (SEG) for deep contact patterns, which is one of the key processes for silicon-based stacked devices and cell switches for next generation memories, was studied. Absolute values of selectivity loss during silicon SEG using the most popular H 2/dichlorosilane (DCS)/HCl gas system were evaluated using a commercialized inspection tool in 200mm wafers with real contact patterns. It was revealed that HCl=(DCS + HCl) ratio and the contact structure played a crucial role in suppressing selectivity loss. The number of selectivity losses in an entire wafer was less than 100 when the HCl=(DCS + HCl) ratio was larger than 0.41. The vertical pn diode prepared using the silicon SEG process with elaborate selectivity control showed more remarkable electrical abilities to accommodate current flow than polycrystalline silicon (poly-Si), including the ideality factor and swing, and reverse leakage current.

Original languageEnglish (US)
Article number08JF03
JournalJapanese Journal of Applied Physics
Volume49
Issue number8 PART 2
DOIs
StatePublished - Aug 2010

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