Abstract
A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 668-671 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Computers |
| Volume | C-20 |
| Issue number | 6 |
| DOIs | |
| State | Published - Jun 1971 |
| Externally published | Yes |
Keywords
- Cascaded adders
- overflow detection and correction
- parallel processing
- serial addition