Abstract
An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure described herein utilizes the idea of cycle borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. The theoretical basis for the procedure is developed, a new algorithm for timing analysis of acyclic pipeline circuits with deliberate skew is presented, and a sensitivity-based optimizer is used to solve the sizing + skew problem. Our experimental results verify that the procedure of cycle borrowing using sizing + skew results in a better overall area-delay tradeoff as compared to using sizing alone. Index Terms - Clocks, CMOS digital integrated circuits, design automation, optimization methods, synchronization, very large scale integration.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 173-182 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 17 |
| Issue number | 2 |
| DOIs | |
| State | Published - 1998 |
Bibliographical note
Funding Information:Manuscript received October 17, 1995; revised May 9, 1997. This work was supported in part by the National Science Foundation through Grant MIP-9502556. This paper was recommended by Associate Editor K. Sakallah. H. Sathyamurthy was with the Department of Electrical and Computer Engineering at Iowa State University, Ames, 50010 USA. He is now with Mentor Graphics, San Jose, CA USA. S. S. Sapatnekar was with the Department of Electrical and Computer Engineering at Iowa State University, Ames, IA 50010 USA. He is now with the University of Minnesota, Minneapolis, MN 55455 USA. J. P. Fishburn is with Lucent Technologies Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0278-0070(98)02548-2.