TY - GEN
T1 - Spin-Hall effect MRAM based cache memory
T2 - 73rd Annual Device Research Conference, DRC 2015
AU - Kim, Jongyeon
AU - Tuohy, Bill
AU - Ma, Cong
AU - Choi, Won Ho
AU - Ahmed, Ibrahim
AU - Lilja, David
AU - Kim, Chris H.
PY - 2015/8/3
Y1 - 2015/8/3
N2 - One of the key objectives of STT-MRAM research has been on minimizing switching current while maintaining the required nonvolatility. To address this challenge, non-traditional MRAMs based on novel switching mechanisms have been proposed. In particular, spin-Hall effect (SHE) which utilizes large spin currents generated in the direction transverse to the charge current have been recently drawing attention [1]. Despite early promises such as lower switching current by means of efficient spin generation (i.e. Ispin/Icharge>100%) and longer device lifetime owing to the decoupled read and write paths, there is still a lack of a comprehensive study for benchmarking SHE-MRAM against other memory technologies. In this work, we explore the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture) to evaluate the feasibility of SHE-MRAM for large on-die cache memory.
AB - One of the key objectives of STT-MRAM research has been on minimizing switching current while maintaining the required nonvolatility. To address this challenge, non-traditional MRAMs based on novel switching mechanisms have been proposed. In particular, spin-Hall effect (SHE) which utilizes large spin currents generated in the direction transverse to the charge current have been recently drawing attention [1]. Despite early promises such as lower switching current by means of efficient spin generation (i.e. Ispin/Icharge>100%) and longer device lifetime owing to the decoupled read and write paths, there is still a lack of a comprehensive study for benchmarking SHE-MRAM against other memory technologies. In this work, we explore the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture) to evaluate the feasibility of SHE-MRAM for large on-die cache memory.
KW - Delays
KW - FinFETs
KW - Integrated circuit modeling
KW - Random access memory
KW - Sensors
KW - Tunneling magnetoresistance
UR - http://www.scopus.com/inward/record.url?scp=84957707575&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84957707575&partnerID=8YFLogxK
U2 - 10.1109/DRC.2015.7175583
DO - 10.1109/DRC.2015.7175583
M3 - Conference contribution
AN - SCOPUS:84957707575
T3 - Device Research Conference - Conference Digest, DRC
SP - 117
EP - 118
BT - 73rd Annual Device Research Conference, DRC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 21 June 2015 through 24 June 2015
ER -