High-performance circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as synthesis, layout (placement and routing), and in-place optimizations performed late in the design cycle. While timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup appears due to the use of simplified delay models, and on account of the fact that its ability to consider the effects of logical interactions between signals is limited. Nevertheless, it has become a mainstay of design over the last few decades; one of the earliest descriptions of a static timing approach can be found in . This chapter will first overview some of the most prominent techniques for Static Timing Analysis (STA). It will then outline issues related to Statistical Static Timing Analysis (SSTA), a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits.
|Original language||English (US)|
|Title of host publication||EDA for IC Implementation, Circuit Design, and Process Technology|
|ISBN (Print)||0849379245, 9780849379246|
|State||Published - Jan 1 2006|