Statistical analysis and design of HARP FPGAs

Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.

Original languageEnglish (US)
Article number1677693
Pages (from-to)2088-2101
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume25
Issue number10
DOIs
StatePublished - Oct 2006

Bibliographical note

Funding Information:
Manuscript received April 12, 2005; revised August 2, 2005. This work was supported in part by the National Science Foundation (NSF) under Contract CAREER CCF-0347891. This paper was recommended by Associate Editor C. J. Alpert.

Keywords

  • Architecture
  • Field programmable gate arrays
  • Integrated circuits
  • Routing

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