Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Drew C. Ness, David J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Radiation induced single-event upsets are becoming an increasing issue for designers due to the impact on overall design reliability. This paper presents a method for translating probabilistic information from lower levels in the design hierarchy into efficient, fast, and useful tools at higher levels. This method allows designers to incorporate soft error reliability analysis into the verification process at greatly reduced simulation expense with high accuracy. We also include metrics to estimate the error in the method. Results from both abstracted verification simulations and Verilog soft error simulations are presented. Our method bridges a gap between low level reliability measurements and high level reliability simulations.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2008
Subtitle of host publicationProceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages297-302
Number of pages6
DOIs
StatePublished - Dec 1 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
Duration: Mar 4 2008Mar 6 2008

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

OtherGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CountryUnited States
CityOrlando, FL
Period3/4/083/6/08

Keywords

  • Fault distribution
  • Reliability analysis
  • SER
  • SEU

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