STEM: A scheme for two-phase evaluation of majority logic

Meghna G. Mankalale, Zhaoxin Liang, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The switching time of a magnet in a spin-current-based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next, in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an $n$-input AND gate that requires a total of ( $2n-1$) inputs in the conventional implementation can now be implemented with only ($n+1$ ) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates is 1.6-3.4$\times$ faster and 1.9-6.9$\times$ more energy efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5$\times$ faster, 2.2 $\times$ more energy efficient, and provides a 16% improvement in area.

Original languageEnglish (US)
Article number7904699
Pages (from-to)606-615
Number of pages10
JournalIEEE Transactions on Nanotechnology
Volume16
Issue number4
DOIs
StatePublished - Jul 2017

Bibliographical note

Funding Information:
Manuscript received February 16, 2017; revised April 3, 2017; accepted April 10, 2017. Date of publication April 19, 2017; date of current version July 7, 2017. This work was supported in part by C-SPIN, one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. The review of this paper was arranged by Associate Editor W. Zhao. (Corresponding author: Meghna G. Mankalale.) The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: manka018@umn.edu; zxliang@umn.edu; sachin@umn.edu).

Publisher Copyright:
© 2002-2012 IEEE.

Keywords

  • All-spin logic
  • majority logic
  • spintronics
  • two-phase logic

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