Switching Characteristics of Scaled CMOS Circuits at 77 K

Performance enhancement of CMOS inverters at room and liquid-nitrogen temperatures are studied. The extent of delay improvement at low temperature is limited by the velocity saturation effect, as the channel lengths are decreased and/or the supply voltage increased. An analytical delay model taking into account velocity saturation is developed that accurately predicts the measured delay of CMOS inverter chains with drawn channel lengths down to 0.5 μm. Compared are the relative merits of CMOS devices operating at 77 K and those scaled for room-temperature operations.