Synthesis of folded pipelined architectures for multirate DSP algorithms

Tracy C. Denk, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms.

Original languageEnglish (US)
Pages (from-to)595-607
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume6
Issue number4
DOIs
StatePublished - 1998

Bibliographical note

Funding Information:
Manuscript received September 15, 1995; revised May 30, 1998. This work was supported by the Advanced Research Projects Agency and the Solid State Electronics Directorate, Wright-Patterson AFB under Contract AF/F33615-93-C-1309. T. C. Denk is with Broadcom Corporation, Irvine, CA 92618 USA. K. K. Parhi is with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 1063-8210(98)07212-6.

Keywords

  • Data flow graphs
  • High-level synthesis
  • Parallel architectures
  • Retiming
  • Signal processing
  • Very large scale integration

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