System-level design for test of fully differential analog circuits

Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


Several designs for test techniques for fully differential circuits have recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in differential circuits. These techniques have not previously been verified experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures. The test chip is a fully differential fifth-order filter, and was fabricated on a 2-μm CMOS process. The test techniques implemented are derived from a system-level technique developed earlier. The test chip contains fault injection circuitry to emulate faults. Our results demonstrate that the FDAC is a viable design for test technique for analog circuits.

Original languageEnglish (US)
Pages (from-to)1526-1534
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number10
StatePublished - Oct 1996

Bibliographical note

Funding Information:
Dr. Vinnakota receibr ed the Career award from the National Science Foundation in 1995.

Funding Information:
Manuscript received October 1, 1995; revised April 20, 1996. This work was supported in part by NSF Grant MIP-9501499. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 001 8-9200(96)07340-4,


Dive into the research topics of 'System-level design for test of fully differential analog circuits'. Together they form a unique fingerprint.

Cite this