Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers

Janardhan H. Satyanarayana, Keshab K Parhi, Leilei Song, Yun Nan Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

This paper presents a systematic theoretical approach for the analysis of bounds on power consumption in Baugh-Wooley, binary tree and Wallace tree multipliers. This is achieved by first developing state transition diagrams (STDs) for the sub-circuits making up the multipliers. The STD is comprised of states and edges, with the edges representing a transition (switching activity) from one state to another in the sub-circuit. Then, maximum (minimum) energy values associated with the edges constituting the STDs are used to derive the upper (lower) bound in both non-pipelined and p-bit-level pipelined multipliers. It is shown that as p is decreased, the upper bound approaches the lower bound. Moreover, based on the theoretical analysis we conclude that the upper bound in a Baugh-Wooley multiplier has a cubic dependence on the word length, while that in a binary tree multiplier has a quadratic dependence on the word length.

Original languageEnglish (US)
Title of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages492-499
Number of pages8
StatePublished - Dec 1 1996
EventProceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA
Duration: Oct 7 1996Oct 9 1996

Other

OtherProceedings of the 1996 International Conference on Computer Design, ICCD'96
CityAustin, TX, USA
Period10/7/9610/9/96

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