This paper presents an approach for systematically synthesizing VLSI architectures for M-ary tree-structured filter banks which are constructed from a prototype M-channel FIR filter bank. The resulting synchronous architecture is single-rate, i.e., the architecture uses a single clock even though it implements a multirate algorithm. We derive folding equations and use retiming for folding multirate systems to synthesize the control circuitry. A scheduling algorithm is presented which retimes the multirate filter bank to keep the memory requirements of the architecture low. Our approach can be used to design architectures for a wide variety of applications of full and pruned tree-structured filter banks including subband decompositions, discrete wavelet transforms, and computation of wavelet packet bases.
|Original language||English (US)|
|Number of pages||10|
|State||Published - Dec 1 1995|
|Event||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn|
Duration: Oct 16 1995 → Oct 18 1995
|Other||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing|
|Period||10/16/95 → 10/18/95|