The estimation of signal stable ranges in a com binational circuit is an important issue for determining clock time in a synchronous system. An optimal clocking period time highly depends on the accuracy of the shortest path length as well as the longest path length in a combinational circuit. In this paper, a sensitization criterion for the short path is first proposed. Based on this sensitization criterion, an accurate model for calculation of signal stable range can be created. This will allow the output stable range of a gate to be the union of its inputs when the input leads hold a controlling value, rather than to be always the intersection as the previous approach  did. Then, an LS-algorithm for calculation of signal stable ranges is presented in which both the sensitizable shortest path and the sensitizable longest path are considered. It avoids the exhaustive search by tracing the path sensitization and eliminates some conservative restriction to get more accurate results in a more efficient way, compared to the previous approaches. The speedup and the improved accuracy of the proposed LS-algorithm showed promising experimental results.
|Original language||English (US)|
|Number of pages||8|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Aug 1994|
Bibliographical noteFunding Information:
Manuscript received December 2, 1991; revised February 22, 1994. This work was supported in part by NSF Grant MIP-9007168 This paper was recommended by Associate Editor R. E. Bryant.. L. R. Liu was with The Department of Computer Science, University of Minnesota; he is now with Actel, Sunnyvale, CA 94086 USA. H.-C. Chen was with The Department of Computer Science, University of Minnesota; he is now with AT&T Bell Labs, Murray Hill, NJ 07974 USA. D. H. C. Du is with the Department of Computer Science, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9400666.