The design and implementation of the IMS A110 image and signal processor

S. R. Barraclough; M. Sotheran; K. Burain; A. P. Wise; A. Vadher; W. R. Robbins; R. M. Forsyth

doi:10.1109/CICC.1989.56826

The design and implementation of the IMS A110 image and signal processor

S. R. Barraclough, M. Sotheran, K. Burain, A. P. Wise, A. Vadher, W. R. Robbins, R. M. Forsyth

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

The IMS A110 provides a solution to many real time image and signal processing problems by supporting techniques such as 1D/2D convolution/ correlation, statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single chip digital signal processing device which operates at 20-MHz with a data throughput of 420 MOPS, and consists of three programmable length shift registers, a configurable 21 stage multiply accumulate array (MAC), a post processing unit (PPU) and a microprocessor interface. The chip is fabricated in a single level metal 1.2um polysilicide CMOS process and contains around 375k transistors on a 9.6mm×8.1mm die which translates to a site density of 4.1 tr/sq. mil. (excluding the pad ring). This paper will present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array.

Original language	English (US)
Article number	5726293
Pages (from-to)	24.5.1-24.5.4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1989.56826
State	Published - Dec 1 1989
Event	11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States Duration: May 15 1989 → May 18 1989

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title = "The design and implementation of the IMS A110 image and signal processor",

abstract = "The IMS A110 provides a solution to many real time image and signal processing problems by supporting techniques such as 1D/2D convolution/ correlation, statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single chip digital signal processing device which operates at 20-MHz with a data throughput of 420 MOPS, and consists of three programmable length shift registers, a configurable 21 stage multiply accumulate array (MAC), a post processing unit (PPU) and a microprocessor interface. The chip is fabricated in a single level metal 1.2um polysilicide CMOS process and contains around 375k transistors on a 9.6mm×8.1mm die which translates to a site density of 4.1 tr/sq. mil. (excluding the pad ring). This paper will present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array.",

author = "Barraclough, {S. R.} and M. Sotheran and K. Burain and Wise, {A. P.} and A. Vadher and Robbins, {W. R.} and Forsyth, {R. M.}",

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AU - Wise, A. P.

AU - Vadher, A.

AU - Robbins, W. R.

AU - Forsyth, R. M.

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AB - The IMS A110 provides a solution to many real time image and signal processing problems by supporting techniques such as 1D/2D convolution/ correlation, statistical/histogram data collection and nonlinear data transformation. It is a cascadable, software configurable single chip digital signal processing device which operates at 20-MHz with a data throughput of 420 MOPS, and consists of three programmable length shift registers, a configurable 21 stage multiply accumulate array (MAC), a post processing unit (PPU) and a microprocessor interface. The chip is fabricated in a single level metal 1.2um polysilicide CMOS process and contains around 375k transistors on a 9.6mm×8.1mm die which translates to a site density of 4.1 tr/sq. mil. (excluding the pad ring). This paper will present an overview of the A110 architecture and highlight the key design techniques used to implement the multiply accumulate array.

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The design and implementation of the IMS A110 image and signal processor

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