The impact of hot carriers on timing in large circuits

Jianxin Fang, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper focuses on hot carrier (HC) effects in large scale digital circuits and proposes a scalable method for analyzing circuit-level delay degradations. At the transistor level, a multi-mode energy-driven model for nanometer technologies is employed. At the logic cell level, a methodology that captures the aging of a device as a sum of device age gains per signal transition is described, and the age gain is characterized using SPICE simulation. At the circuit level, the cell-level characterizations are used in conjunction with probabilistic methods to perform fast degradation analysis. The proposed analysis method is validated by Monte Carlo simulation on various benchmark circuits, and is proved to be accurate, efficient and scalable.

Original languageEnglish (US)
Title of host publicationASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages591-596
Number of pages6
DOIs
StatePublished - Apr 26 2012
Event17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
Duration: Jan 30 2012Feb 2 2012

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
CountryAustralia
CitySydney, NSW
Period1/30/122/2/12

Fingerprint Dive into the research topics of 'The impact of hot carriers on timing in large circuits'. Together they form a unique fingerprint.

Cite this