TY - GEN
T1 - The synthesis of linear finite state machine-based stochastic computational elements
AU - Li, Peng
AU - Qian, Weikang
AU - Riedel, Marc
AU - Bazargan, Kia
AU - Lilja, David J
PY - 2012
Y1 - 2012
N2 - The Stochastic Computational Element (SCE) uses streams of random bits (stochastic bits streams) to perform computation with conventional digital logic gates. It can guarantee reliable computation using unreliable devices. In stochastic computing, the linear Finite State Machine (FSM) can be used to implement some sophisticated functions, such as the exponentiation and tanh functions, more efficiently than combinational logic. However, a general approach about how to synthesize a linear FSM-based SCE for a target function has not been available. In this paper, we will introduce three properties of the linear FSM used in stochastic computing and demonstrate a general approach to synthesize a linear FSM-based SCE for a target function. Experimental results show that our approach produces circuits that are much more tolerant of soft errors than deterministic implementations, while the area-delay product of the circuits are less than that of deterministic implementations.
AB - The Stochastic Computational Element (SCE) uses streams of random bits (stochastic bits streams) to perform computation with conventional digital logic gates. It can guarantee reliable computation using unreliable devices. In stochastic computing, the linear Finite State Machine (FSM) can be used to implement some sophisticated functions, such as the exponentiation and tanh functions, more efficiently than combinational logic. However, a general approach about how to synthesize a linear FSM-based SCE for a target function has not been available. In this paper, we will introduce three properties of the linear FSM used in stochastic computing and demonstrate a general approach to synthesize a linear FSM-based SCE for a target function. Experimental results show that our approach produces circuits that are much more tolerant of soft errors than deterministic implementations, while the area-delay product of the circuits are less than that of deterministic implementations.
UR - http://www.scopus.com/inward/record.url?scp=84859989188&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84859989188&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2012.6165056
DO - 10.1109/ASPDAC.2012.6165056
M3 - Conference contribution
AN - SCOPUS:84859989188
SN - 9781467307727
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 757
EP - 762
BT - ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
T2 - 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Y2 - 30 January 2012 through 2 February 2012
ER -