Timing analysis of combinational circuits containing complex gates

Current timing analysis tools deal with combinational circuit composed of primitive gates. In this paper, we are investigating ways to do timing analysis of combinatorial circuits with complex gates. Two possible approaches are proposed. The first approach is to design path sensitization criterion for circuits which is composed of complex gates. Another approach is first to transform complex gates to primitive gates and then using existing tools to perform timing analysis. A sensitization criterion is proposed for general complex gates where the functionality and delay information are given. Two commonly used complex gates, XOR and multiplexer, are examined and simplified sensitization criteria are generated. The gate expansion is performed on different delay models to show the compatibility between the original circuit and the transformed one. A general gate expansion algorithm is provided in this paper which can be used for general complex gates. From the experiment, we learned that the first approach can be performed in less computation time than the second one. The circuit delay obtained with the first approach is also smaller and more accurate than that obtained by the second approach.