Timing minimization by statistical timing hMetis-based partitioning

Cristinel Ababei, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper we present statistical timing driven hMetis-based partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing criticality concept to change the partitioning process itself. We exploit the hyperedge coarsening scheme of the hMetis partitioner for our timing minimization purpose. This allows us to perform partitioning such that the most critical nets in the circuit are not cut and therefore timing minimization can be achieved. The use of the hMetis partitioning algorithm makes our partitioning methodology fast. Simulations results show that 22% average delay improvement can be obtained. Furthermore, as a result of using the statistical timing model, the partitioning results can tolerate changes in temperature and process variation, hence causing less delay change compared to partitioning using static timing models.

Original languageEnglish (US)
Title of host publicationProceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
PublisherIEEE Computer Society
Pages58-63
Number of pages6
ISBN (Electronic)0769518680
DOIs
StatePublished - Jan 1 2003
Event16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design - New Delhi, India
Duration: Jan 4 2003Jan 8 2003

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2003-January
ISSN (Print)1063-9667

Other

Other16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design
Country/TerritoryIndia
CityNew Delhi
Period1/4/031/8/03

Keywords

  • Delay
  • Integrated circuit interconnections
  • Libraries
  • Minimization
  • Partitioning algorithms
  • Process design
  • Process planning
  • Programmable logic arrays
  • Timing
  • Wire

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