@inproceedings{8b08bdb0eb2c433fb2b51fb5aa97ecdb,
title = "Variation aware performance analysis of gain cell embedded DRAMs",
abstract = "Gain cell embedded DRAMs are twice as dense as 6T SRAMs, are logic compatible, have decoupled read and write paths providing good low voltage margin, and can drive long bitlines with gain. In this work, we present a variation study of gain cell eDRAM performance using an industrial 1.2V, 65nm low power CMOS process. Two methods are proposed to analyze eDRAM performance which can be used for designing variation tolerant eDRAM circuits, developing redundancy techniques, and guiding the device optimization procedure.",
keywords = "Bitline delay, Embedded DRAM, Gain cell, Monte Carlo simulation, Process variation",
author = "Wei Zhang and Chun, {Ki Chul} and Kim, {Chris H.}",
year = "2010",
doi = "10.1145/1840845.1840850",
language = "English (US)",
isbn = "9781450301466",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "19--24",
booktitle = "ISLPED'10 - Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design",
note = "16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10 ; Conference date: 18-08-2010 Through 20-08-2010",
}