TY - GEN
T1 - Verifying equivalence of digital signal processing circuits
AU - Parhi, Keshab K.
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Verifying the equivalence of digital signal processing circuits is not only important in designing architectures, but also in designing secure circuits. If the functionality equivalence cannot be easily verified, then the security can be improved. In this paper, we present novel use of high-level transformations to hide the functionalities of DSP circuits, which include retiming, pipelining, folding, unfolding, and interleaving. We show that we can design circuits which are harder to reverse engineer by adopting high-level transformations. However, other techniques, such as modifying the switch instances, adding dummy loops, and manipulating inputs, can also be exploited for both verifying equivalence as well as designing secure circuits.
AB - Verifying the equivalence of digital signal processing circuits is not only important in designing architectures, but also in designing secure circuits. If the functionality equivalence cannot be easily verified, then the security can be improved. In this paper, we present novel use of high-level transformations to hide the functionalities of DSP circuits, which include retiming, pipelining, folding, unfolding, and interleaving. We show that we can design circuits which are harder to reverse engineer by adopting high-level transformations. However, other techniques, such as modifying the switch instances, adding dummy loops, and manipulating inputs, can also be exploited for both verifying equivalence as well as designing secure circuits.
KW - Functionality Equivalence
KW - Hierarchical Folding
KW - High-Level Transformation
KW - Reverse Engineering
KW - Security
UR - http://www.scopus.com/inward/record.url?scp=84876252958&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876252958&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2012.6488967
DO - 10.1109/ACSSC.2012.6488967
M3 - Conference contribution
AN - SCOPUS:84876252958
SN - 9781467350518
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 99
EP - 103
BT - Conference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
T2 - 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
Y2 - 4 November 2012 through 7 November 2012
ER -