This paper considers the implementation of video data format converters using a minimum number of registers. A systematic lifetime analysis of the variables is carried out to determine the latency and the minimum number of registers needed for the converter. The technique of obtaining the minimum number of registers is illustrated using four classes of data format converters: line-by-line to column-by-column, line-by-line to interleaved skewed one-dimensional block format, line-by-line to interleaved two-dimensional block format, and line-by-line to zigzag format. Closed-form expressions for minimum number of registers in these converters are obtained in terms of the number of input and output pixels processed per cycle and the number of input and output bits processed per pixel in a cycle.
|Original language||English (US)|
|Number of pages||13|
|Journal||IEEE Transactions on Circuits and Systems for Video Technology|
|State||Published - Jun 1992|