Abstract
An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm2, and consumes 0.5 mW of power.
Original language | English (US) |
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Pages (from-to) | 978-981 |
Number of pages | 4 |
Journal | Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference |
DOIs | |
State | Published - 2009 |
Event | 31st Annual International Conference of the IEEE Engineering in Medicine and Biology Society: Engineering the Future of Biomedicine, EMBC 2009 - Minneapolis, MN, United States Duration: Sep 2 2009 → Sep 6 2009 |
PubMed: MeSH publication types
- Evaluation Study
- Journal Article
- Research Support, Non-U.S. Gov't