Barrier synchronization constructs are placed between phases of parallel programs to ensure correctness in the execution - by preventing threads from proceeding to the subsequent phases of the program before all threads have completed the preceding stage(s). Upon release, threads leaving the barrier at the same time cause sudden change in activity that can potentially lead to voltage emergencies in the form of timing errors, due to electrical properties of power delivery network. In this paper, we demonstrate how approximation through barrier relaxation - i.e., letting threads proceed past barriers without waiting for the others, and thereby preventing abrupt activity changes - can help prevent voltage emergencies.
Bibliographical noteFunding Information:
This work was supported in part by NSF Grant no. CCF-1438286.
© 2002-2011 IEEE.
- Approximate barrier synchronization
- relaxed synchronization
- timing errors
- voltage noise