Wafer-level 3D integration technology

Steven J. Koester, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan Neng Chen, Douglas C. La Tulipe, Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis

Research output: Contribution to journalReview articlepeer-review

131 Scopus citations

Abstract

An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

Original languageEnglish (US)
Pages (from-to)583-597
Number of pages15
JournalIBM Journal of Research and Development
Volume52
Issue number6
DOIs
StatePublished - Jan 1 2008

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