Abstract
With the increasing influence of the resistive effects of interconnects on the performance of VLSI systems, a greater stress is being laid on careful interconnect design. One prominent technique is the approach of sizing wires for long interconnects to achieve the desired speed and power characteristics [1-4]. It has also been suggested that one may appropriately insert repeaters [5] for significant delay reductions. This paper unifies these approaches to optimizing an interconnect by placing a prespecified number of buffers (drivers and repeaters) using a dynamic programming procedure and then performing simultaneous wire and buffer sizing using a sensitivity-based heuristic. Experimental results are presented to prove the utility and performance of the approach.
Original language | English (US) |
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Title of host publication | Proceedings of the IEEE International Conference on VLSI Design |
Publisher | IEEE |
Pages | 346-351 |
Number of pages | 6 |
State | Published - Jan 1 1996 |
Event | Proceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India Duration: Jan 3 1996 → Jan 6 1996 |
Other
Other | Proceedings of the 1996 9th International Conference on VLSI Design |
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City | Bangalore, India |
Period | 1/3/96 → 1/6/96 |