TY - JOUR
T1 - A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition
AU - Wu, Tong
AU - Xu, Jian
AU - Lian, Yong
AU - Khalili, Azam
AU - Rastegarnia, Amir
AU - Guan, Cuntai
AU - Yang, Zhi
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/2
Y1 - 2016/2
N2 - In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.
AB - In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.
KW - EC-PC regression
KW - multichannel digital system
KW - neural signal processing
KW - unsupervised spike detection
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U2 - 10.1109/TBCAS.2015.2389266
DO - 10.1109/TBCAS.2015.2389266
M3 - Article
C2 - 25769170
AN - SCOPUS:84924560325
SN - 1932-4545
VL - 10
SP - 3
EP - 17
JO - IEEE transactions on biomedical circuits and systems
JF - IEEE transactions on biomedical circuits and systems
IS - 1
M1 - 7055372
ER -