A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier

Bodhisatwa Sadhu; Mark A. Ferriss; Jean Olivier Plouchart; Arun S. Natarajan; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Scott Reynolds; Aydin Babakhani; Soner Yaldiz; Larry Pileggi; Ramesh Harjani; Jose Tierno; Daniel Friedman

doi:10.1109/RFIC.2012.6242235

A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier

Bodhisatwa Sadhu, Mark A. Ferriss, Jean Olivier Plouchart, Arun S. Natarajan, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Scott Reynolds, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Jose Tierno, Daniel Friedman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Scopus citations

Abstract

This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of -130dBc/Hz at 10MHz offset from a 22GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 500 measurements across PVT variations validate the proposed PLL design: phase noise variation across 46 dies for 3 different frequencies is σ < 0.6dB, across supply variation over 0.7-1.5V is 2dB and across 80°C temperature variation is 2dB. At the 25GHz center frequency, the VCO FOM _T is 188dBc/Hz.

Original language	English (US)
Title of host publication	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
Pages	75-78
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2012.6242235
State	Published - 2012
Event	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Montreal, QC, Canada Duration: Jun 17 2012 → Jun 19 2012

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Other

Other	2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
Country/Territory	Canada
City	Montreal, QC
Period	6/17/12 → 6/19/12

Keywords

60GHz
PLL
VCO
phase noise
transconducance linearization
tuning range

Access

10.1109/RFIC.2012.6242235

OpenUrl availability

Full text

Cite this

Sadhu, B., Ferriss, M. A., Plouchart, J. O., Natarajan, A. S., Rylyakov, A. V., Valdes-Garcia, A., Parker, B. D., Reynolds, S., Babakhani, A., Yaldiz, S., Pileggi, L., Harjani, R., Tierno, J., & Friedman, D. (2012). A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. In 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers (pp. 75-78). Article 6242235 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2012.6242235

A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. / Sadhu, Bodhisatwa; Ferriss, Mark A.; Plouchart, Jean Olivier et al.
2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers. 2012. p. 75-78 6242235 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sadhu, B, Ferriss, MA, Plouchart, JO, Natarajan, AS, Rylyakov, AV, Valdes-Garcia, A, Parker, BD, Reynolds, S, Babakhani, A, Yaldiz, S, Pileggi, L, Harjani, R, Tierno, J & Friedman, D 2012, A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. in 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers., 6242235, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, pp. 75-78, 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012, Montreal, QC, Canada, 6/17/12. https://doi.org/10.1109/RFIC.2012.6242235

Sadhu B, Ferriss MA, Plouchart JO, Natarajan AS, Rylyakov AV, Valdes-Garcia A et al. A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. In 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers. 2012. p. 75-78. 6242235. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). doi: 10.1109/RFIC.2012.6242235

Sadhu, Bodhisatwa ; Ferriss, Mark A. ; Plouchart, Jean Olivier et al. / A 21.8-27.5GHz PLL in 32nm SOI using G _m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers. 2012. pp. 75-78 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

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abstract = "This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of -130dBc/Hz at 10MHz offset from a 22GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 500 measurements across PVT variations validate the proposed PLL design: phase noise variation across 46 dies for 3 different frequencies is σ < 0.6dB, across supply variation over 0.7-1.5V is 2dB and across 80°C temperature variation is 2dB. At the 25GHz center frequency, the VCO FOM T is 188dBc/Hz.",

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