A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS

Jean Olivier Plouchart; Mark A. Ferriss; Arun S. Natarajan; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander Rylyakov; Benjamin D. Parker; M. Beakes; Aydin Babakhani; Soner Yaldiz; Larry Pileggi; Ramesh Harjani; Scott Reynolds; Jose A. Tierno; Daniel Friedman

doi:10.1109/TCSI.2013.2265961

A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS

Jean Olivier Plouchart, Mark A. Ferriss, Arun S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, M. Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose A. Tierno, Daniel Friedman

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

Original language	English (US)
Article number	6541965
Pages (from-to)	2009-2017
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	60
Issue number	8
DOIs	https://doi.org/10.1109/TCSI.2013.2265961
State	Published - 2013

Keywords

Millimeter wave integrated circuits
phase locked loops
phase noise
silicon-on-insulator

Access

10.1109/TCSI.2013.2265961

OpenUrl availability

Full text

Cite this

Plouchart, J. O., Ferriss, M. A., Natarajan, A. S., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B. D., Beakes, M., Babakhani, A., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., & Friedman, D. (2013). A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(8), 2009-2017. Article 6541965. https://doi.org/10.1109/TCSI.2013.2265961

Plouchart, JO, Ferriss, MA, Natarajan, AS, Valdes-Garcia, A, Sadhu, B, Rylyakov, A, Parker, BD, Beakes, M, Babakhani, A, Yaldiz, S, Pileggi, L, Harjani, R, Reynolds, S, Tierno, JA & Friedman, D 2013, 'A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 8, 6541965, pp. 2009-2017. https://doi.org/10.1109/TCSI.2013.2265961

@article{baea0dcae94e414c9bc9373175cae90a,

title = "A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS",

abstract = "A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.",

keywords = "Millimeter wave integrated circuits, phase locked loops, phase noise, silicon-on-insulator",

author = "Plouchart, {Jean Olivier} and Ferriss, {Mark A.} and Natarajan, {Arun S.} and Alberto Valdes-Garcia and Bodhisatwa Sadhu and Alexander Rylyakov and Parker, {Benjamin D.} and M. Beakes and Aydin Babakhani and Soner Yaldiz and Larry Pileggi and Ramesh Harjani and Scott Reynolds and Tierno, {Jose A.} and Daniel Friedman",

year = "2013",

doi = "10.1109/TCSI.2013.2265961",

language = "English (US)",

volume = "60",

pages = "2009--2017",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

number = "8",

}

TY - JOUR

T1 - A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS

AU - Plouchart, Jean Olivier

AU - Ferriss, Mark A.

AU - Natarajan, Arun S.

AU - Valdes-Garcia, Alberto

AU - Sadhu, Bodhisatwa

AU - Rylyakov, Alexander

AU - Parker, Benjamin D.

AU - Beakes, M.

AU - Babakhani, Aydin

AU - Yaldiz, Soner

AU - Pileggi, Larry

AU - Harjani, Ramesh

AU - Reynolds, Scott

AU - Tierno, Jose A.

AU - Friedman, Daniel

PY - 2013

Y1 - 2013

N2 - A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

AB - A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

KW - Millimeter wave integrated circuits

KW - phase locked loops

KW - phase noise

KW - silicon-on-insulator

UR - http://www.scopus.com/inward/record.url?scp=84881096833&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84881096833&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2013.2265961

DO - 10.1109/TCSI.2013.2265961

M3 - Article

AN - SCOPUS:84881096833

SN - 1549-8328

VL - 60

SP - 2009

EP - 2017

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 8

M1 - 6541965

ER -

A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS

Abstract

Keywords

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this