A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jun 25 2013|
- Millimeter wave integrated circuits
- phase locked loops
- phase noise